AI Repricing the Factory Bill of Materials: Macronix, MemFlation and the New Memory Tiers
Quotations for a motor controller, an in-vehicle gateway or a machine-vision edge box are being rewritten by a line item most plants stopped tracking years ago: small-capacity nonvolatile memory. Nothing collapsed on the factory side. What changed is where the world's memory capacity is pointed — Samsung, SK Hynix and Micron have steered wafers and capital toward high-bandwidth memory (HBM) and advanced server configurations over the past year, and the shortfall has landed on NOR flash, SLC NAND and eMMC, the parts engineers specify for boot code, firmware and system control. Martin Lin, director of marketing at Macronix International, told EE Times Taiwan that the issue is not simply more demand for the same parts, because “the entire memory architecture is changing.”
Case in Point: What One AI Rack Says About Demand
Start with a concrete unit of observation: the flash count inside a rack. In AI servers these devices handle boot-up, firmware, system control and security. As baseboard management controllers (BMCs), network switches and other control elements proliferate, the tally grows fast. Lin noted that conventional servers typically required only about three to five flash devices, while AI servers need considerably more, so per-rack flash consumption climbs sharply with each hardware generation.
His own comparison is blunt: “The previous-generation rack had around 600 to 800 devices. The latest generation now has more than 1,000”.
Why This Cycle Is Structural Rather than Cyclical
Macronix frames the moment as the biggest re-ordering of the memory industry in decades, and its answer is investment rather than price talk. The company raised 2026 capital expenditure to NT$37.8 billion, funding 12-inch wafer expansion aimed at rising demand for 3D NOR, NAND and eMMC products, while design targets shift to denser, lower-power and more reliable parts.
The mechanics matter to purchasing teams. HBM and advanced server memory absorb capacity that previously served mature process nodes, and AI-oriented bookings run well into 2027; enterprise solid-state drives (SSDs) for AI data centers pull NAND in the same direction. What is left for specialty products is a narrower base, so lead times stretch even in end markets where volumes are flat. Independent analyses published during 2026 have pointed to AI infrastructure taking an unusually large share of global memory output, and distributor commentary now treats memory as a structural design risk instead of a predictable commodity line item. For engineering managers expected to hold a bill of materials constant for seven to ten years, that change of framing is the real news.
Reading the Numbers: Price-Led Growth, Not Volume-Led Growth
By the market figures Macronix cites, the memory market passed $20 billion in 2025 and may approach $70 billion in 2026. Because mature-process capacity stays constrained, an increasing share of that expansion comes from price rather than units shipped — a phenomenon the company labels “memory inflation”, or MemFlation.
Supply-side restructuring, rather than a demand spike, has pushed memory prices up sixfold over the past year, and the trend has not broken.
For the categories industrial buyers actually order, pricing is expected to step up again in the third and fourth quarters of 2026 and then hold at elevated levels. Adding fabs does not shorten that window: installing tools, qualifying processes and ramping yield can take two to three years, sometimes longer, so the supply gap cannot be closed quickly. With AI demand continuing to crowd out mature-process capacity, automotive-market supply constraints and pricing pressure should become more visible starting in 2027 — a direct hit for vehicle and industrial electronics programs with long qualification cycles.
Within specialty flash, Macronix expects the combined market for NOR flash, SLC NAND and low-capacity eMMC (≤32GB) to expand significantly, landing at around $24 billion in 2026 on higher shipments plus scarcity-driven pricing. The sub-segments diverge, however. NOR sees the milder moves, cushioned by capacity invested earlier, while SLC NAND and eMMC stay the tightest of the group.
Beyond HBM: Hunting a Middle Tier
Rack device counts capture a change in “quantity”. A second, deeper change is architectural.
Training and inference lean on HBM for the bandwidth GPUs require, yet as models scale, HBM capacity and cost become the limiting factors. Lin's assessment is that “only HBM is fast enough” today, but stacking more HBM layers and adding capacity also raises costs, which is why the industry is searching for memory tiers beyond HBM that offer greater capacity and better cost efficiency.
High-bandwidth flash (HBF) is one candidate. Built on 3D NAND and paired with high-speed interfaces and high-density packaging, it tries to balance bandwidth, capacity and cost by relocating data that does not need to stay in HBM into higher-capacity, relatively lower-cost NAND flash. In parallel, work on AI server architectures that use SSDs with a high level of input/output per second (IOPS) puts low-latency SLC NAND in charge of absorbing the random data accesses GPUs generate, improving utilization. The same pattern shows up in inference software beyond the memory vendors: frameworks increasingly park cache and cold context in lower storage tiers so accelerator-side memory is spent on hot data.
Tiering matters most for inference. Large language models (LLMs) and agentic AI workloads must continuously retain conversation, task and historical information, so KV cache keeps growing. Citing continuous AI conversations, Lin warned that if memory capacity is insufficient, “you have to discard the earlier information.” The remedy is a policy layer: sort data by age, access frequency and latency requirements, keeping the most frequently accessed and latency-sensitive portion in HBM while larger volumes that tolerate slower access migrate to flash, SSDs and other tiers. That is exactly the ground Macronix covered at the recent Future Memory and Storage conference (FMS 2026) in the United States, where it presented a dual-tier SSD architecture aimed at KV cache offloading.
| Tier role | Technology candidates | Implication for system designers |
|---|---|---|
| Hottest, latency-critical | HBM | Top performance at the highest cost, with scarcest allocation |
| Middle, random-access heavy | HBF, low-latency SLC NAND, high-IOPS SSD | Capacity and cost relief, plus a fresh qualification workload |
| Bulk, tolerant of slower access | NAND flash, SSDs, eMMC | Where aging context and KV cache can be parked |
Data Movement, Not FLOPs, Sets the Ceiling
As accelerators keep gaining compute capability, the constraint migrates from raw speed to whether data arrives on time. Lin's phrasing: “The GPU is already fast enough, but now , memory is actually too slow”.
Repeated transfers among CPU, GPU, HBM, DRAM and storage devices consume bandwidth and add latency and power consumption, so raising processor speed alone may not lift system performance in any meaningful way. Cutting that cost has revived memory-centric AI and processing-in-memory (PIM) designs, which move some computation closer to memory and, in certain cases, let memory carry out simple operations before outputting results. The vocabulary is older than the trend: Macronix Chairman and CEO Miin Wu proposed “Memory-centric AI” as early as 2019, and as models, datasets and inference workloads expand, the idea is again drawing attention from industry and academia. In Lin's view, the next stage of AI performance gains will rest not only on faster GPUs but also on more efficient memory architectures, pushing development beyond compute speed toward where data sits, how it moves and when it is processed.
Product Roadmap: Density, Low Power, High Reliability
Architecture is steering silicon. Beyond supplying more high-density NOR flash for AI servers, Macronix is widening its NAND and eMMC portfolios and advancing 3D NAND technology across a broader range of capacities and applications. Mass production today covers 48-layer and 96-layer 3D NAND, with higher-layer-count technologies in development. On the NOR side, density, power consumption and reliability are the design targets, and the process path runs from 55nm to 42nm, with 3D NOR also under development. AI servers already take its high-density NOR flash, and the push into high-reliability markets spans automotive, communications, medical and aerospace. For power budgets in AI, industrial and embedded systems, the low-voltage lineup advances from 3V and 1.8V toward 1.2V.
Macronix’s three major flash product lines continue to evolve toward higher density and greater capacity.
| Product line | Direction of travel | Milestones and functions |
|---|---|---|
| NOR flash | Density, power efficiency and reliability | Steps from 55nm to 42nm; 42nm in 2027 and 3D-32-layer in 2028; boot, firmware, control, security |
| SLC NAND | Long-term supply support | Low-latency handling of AI random-access patterns |
| eMMC | Higher capacity and density | Scaling from 3D-48 and 96 layers to 192 layers |
Common Misreadings Worth Dropping
- “This is another inventory cycle.” It is a capacity reallocation: HBM, advanced server memory and enterprise SSDs are absorbing mature-process resources, so specialty flash flexibility shrinks even when inventories appear normal.
- “Any small-capacity flash can be swapped in.” Boot, firmware and security roles in automotive, medical, aerospace and industrial designs carry long qualification paths; substitution is an engineering project, not a purchasing click.
- “AI only buys HBM, so our parts are safe.” The jump from three to five devices per conventional server to far higher per-rack counts lands on exactly the categories embedded teams buy.
- “Faster GPUs will fix inference economics.” Data movement, not compute, is becoming the binding constraint on latency and energy.
- “New fabs relieve next year.” Tool installation, process qualification and yield ramp mean two to three years between a capital decision and deliverable wafers.
Action Recommendations for Operations and Engineering Leads
- Re-baseline the memory lines of every active BOM. List all NOR flash, SLC NAND and low-capacity eMMC (≤32GB) entries by package, temperature grade and qualification status before quoting price exposure.
- Extend contracting windows. Treat the third and fourth quarters of 2026 as a repricing phase that carries into the following year, and align customer escalators accordingly.
- Qualify a second source before allocation starts. Where pin-compatible alternatives are unproven, begin reliability and software-port work now; long-life industrial and automotive programs should plan around elevated pricing rather than reversal.
- Design for tiering and for power. Reserve latency and energy budget for data movement, and read the low-voltage path from 3V to 1.8V and on to 1.2V as an edge-AI power lever rather than a spec detail.
- Watch capacity signals through a two-year lens. Announcements such as Macronix’s NT$37.8 billion 2026 capex and its 12-inch expansion describe supply that arrives late in the decade, not relief next quarter.
- Put memory on the risk register. Assign joint ownership across purchasing, engineering and product management, because architecture, availability and cost now move together.
FAQ
Why should an industrial buyer care about HBM at all?
Because HBM competes for the same wafers, tool slots and capital that supply the NOR flash, SLC NAND and eMMC used in control boards, HMIs and gateways.
Is MemFlation just general electronics inflation?
No. Macronix applies the term “memory inflation”, or MemFlation, to price-led growth in a market where volume is flat or constrained because the supply structure has tightened.
What is KV cache and why does it need storage tiers?
It is the conversation, task and historical state inference workloads must retain. When capacity runs short, earlier context is dropped, so systems push less frequently used data into flash and SSD tiers while the latency-critical slice stays close to the GPU.
When does pressure ease for automotive and industrial supply?
Not soon. Tight supply and demand conditions are expected to remain difficult to ease, with automotive supply constraints and pricing pressure becoming more visible starting in 2027.
Where can engineers see the roadmap firsthand?
Macronix is bringing its latest nonvolatile memory technologies and application solutions — including automotive electronics and edge AI — to electronica 2026.
The Bottom Line for the Shop Floor
Memory has stopped behaving like background commodity silicon and started behaving like an architecture decision with a long supply-chain tail. Balancing demand from AI servers, gaps in mature flash products and next-generation technology development will define how vendors compete in the next stage, and buyers will be measured by how early they re-qualified their designs. The nearest public checkpoint is electronica 2026, running November 10–13 in Munich, Germany, at Hall C5, Stand 279. Data requests and corrections on this report can go to the Industrial Weekly desk at news@industrialweekly.com.
Written by Michael Torres, Industrial Weekly.